Semiconductor integrated circuit

ABSTRACT

A delay circuit includes a constant current source, a delay stage, and a compensating circuit. The delay circuit may compensate for a variation in a delay characteristic of the delay stage due to a variation in temperature, supply voltage and/or process.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent applicationNo. 2003-350288 filed on Oct. 9, 2003, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuithaving a delay circuit, and particularly to a technique for reducingdependence of a delay characteristic of the delay circuit on variationsin power supply voltage and temperature and process variations, forexample, a technique effective if applied to a semiconductor memorydevice or the like such as a flash memory which performs a readoperation using a timing signal generated by the delay circuit.

SUMMARY OF THE INVENTION

A patent document 1 (Japanese Unexamined Patent Publication No. Hei7(1995)-262781) has taken notice that when a pulse width of a signalbecomes narrow under the influence of a variation in power supplyvoltage, a variation in temperature and process variations, an operationmargin is reduced, whereas when the signal pulse width becomes large,the highest operating frequency of a circuit becomes low, and therebyhas proposed, for example, a circuit which applies a potential foradjusting a delay time to a delay circuit which generates a reset signaldelayed a predetermined time in a self reset circuit to thereby make thedelay time constant without recourse to a power supply voltage,temperatures and variations in manufacture. In order to form a potentialfor adjusting a delay, the delay circuit is placed in a feedback loop, aclock signal generated by the feedback loop or its divided clock signalis phase-compared with a standard clock signal, the voltagecorresponding to the difference in phase is generated by a charge pump,and an operating current of the delay circuit is negative-feedbackcontrolled by its control voltage, thereby causing a signal pulse widthto be generated to follow the cycle of the standard clock signal. Thus,the dependence of a delay characteristic of the delay circuit on thevariation in power supply voltage, the variation in temperature and theprocess variations becomes small.

The present inventors have discussed the dependence of a delaycharacteristic of a delay circuit for generating a sense amplifier starttiming on a variation in power supply voltage, a variation intemperature and process variations, in a flash memory (on-chip flashmodule) on-chipped to a microcomputer. The process variations exert aninfluence on the threshold voltage of a transistor. Since the dependenceon the variation in power supply voltage, the variation in temperatureand the process variations is large in a mere inverter delay circuit, amargin sufficient for a sense operation cannot be ensured if a delay issmall, whereas if the delay is excessively large, an operating speed isreduced. The above known art needs a divider, a phase comparator and acharge pump to generate a delay time adjustment or control potential,thus causing an increase in circuit area. Further, a standard clock isneeded and a crystal oscillator or the like is required to generate it,so that the number of circuit's parts increases too.

An object of the present invention is to provide a semiconductorintegrated circuit equipped with a delay circuit in which dependence ona variation in power supply voltage, a variation in temperature andprocess variations is low.

The above, other objects and novel features of the present inventionwill become apparent from the description of the specification and theaccompanying drawings.

Summaries of representative ones of the inventions disclosed in thepresent application will be explained in brief as follows:

[1] A semiconductor integrated circuit has a delay circuit. The delaycircuit has a constant current source, a delay stage which determines anoperation delay time of an output relative to an input, depending on aconstant current produced by the constant current source, and acompensating circuit which compensates for a variation in delaycharacteristic of the delay stage due to a variation in temperature, avariation in power supply voltage and process variations in the oppositedirection. If all semiconductor switch elements constituting the delaystage are of ideal elements which are not placed under the influence ofchanges or variations in temperature, power supply voltage and thresholdvoltage, then a delay circuit free of delay variations can be realizedby using the constant current source. However, characteristics such ason resistances and threshold voltages are actually affected by thevariations in temperature and power supply voltage and the processvariations so that a delay characteristic varies. The compensatingcircuit compensates for the variation in delay characteristic in theopposite direction. That is, the compensating circuit controls a delayspeed with such a current that a current characteristic with respect tothe power supply voltage, temperature and threshold voltage becomesopposite to a device characteristic of each MOS transistor or the likeof the delay stage. For example, a current that flows through theconstant current source is set as Iconst, and a current at a constantcurrent node is set as the sum of a current Ip and a current Id. Idindicates a current that flows through the compensating circuit. Thecurrent Ip is mirror-reflected on the delay stage as its operatingcurrent. When the on resistance and threshold voltage characteristics ofthe compensating circuit and delay stage vary under the influence of thevariations in temperature and power supply voltage or the like, thecurrent Id changes following it but the current Ip changes so as tocancel it. This is because Iconst=Ip+Id. As a result, the delay stagechanges in its delay characteristic such that the influences such as thevariations in temperature and power supply voltages at that time arecanceled out, and suppresses a variation in delay time. In general, acircuit that needs a given amount of delay is configured of a delaycircuit and other logic section (decode section or the like forselecting a mode or the like). A given amount of delay is often neededin total. Thus, the delay circuit is configured of MOS transistorsidentical to other logic section, whereby the compensating element canbe adjusted such that the total delay becomes constant.

[2] As a specific form of the present invention, the delay stage can beconfigured of inverter type circuits wherein current control transistorswhose each mutual conductance is determined depending on the constantcurrent produced by the constant current source, and switchingtransistors switched in response to the input signal are arranged inseries. At this time, a load transistor connected in parallel with thecompensating circuit is provided at a constant current node of theconstant current source. And a current that flows through the loadtransistor may preferably be mirror-reflected on the transistors whoseeach mutual conductance is determined depending on the constant current.

As a specific form of the compensating circuit, an active element whichassumes a characteristic variation opposite to a variation in devicecharacteristic of the delay stage due to the variation in temperature,the variation in power supply voltage and the process variations, may beadopted. When a change in the characteristic of each transistor placedin a path that causes a current to flow from a power supply terminal ofthe delay stage to its output terminal is a main factor for a variationin delay time, the active element may be intended for compensation ofthe current that flows from the power supply terminal of the delay stageto the output terminal. When a change in the characteristic of eachtransistor placed in a path that causes a current to flow from theoutput terminal of the delay stage to a circuit's ground terminal is ofthe main factor for the variation in delay time, the active element maybe intended for compensation of the current that flows from the outputterminal of the delay stage the circuit's ground terminal. The activeelement may be configured so as to be intended for compensation of thetwo referred to above.

The constant current does not mean a complete constant current.Quantitatively speaking, the variation in the characteristic of theconstant current source due to the variation in temperature, thevariation in power supply voltage and the process variations can bedefined as being smaller than the variation in the characteristic of thedelay stage due to the variation in temperature, the variation in powersupply voltage and the process variations and smaller than the variationin the characteristic of the compensating circuit due to the variationin temperature, the variation in power supply voltage and the processvariations. The need for to which extent the variation in thecharacteristic of the constant current source should be reduced, may bedetermined in consideration of a demand from the whole semiconductorintegrated circuit to which the present invention is applied.

[3] As a further specific form of the present invention, the delay stagemay be complementary MOS inverter type circuits in which p channel typecurrent control MOS transistors and n channel type current control MOStransistors whose mutual conductances are determined depending on theconstant current produced by the constant current source, and p channeltype switching MOS transistors and n channel type switching MOStransistors switched in response to an input signal are arranged inseries.

At this time, a load MOS transistor used as a current source MOStransistor for a current mirror connected in parallel with thecompensating circuit is provided at a constant current node of theconstant current source. A current that flows through the loadtransistor is mirror-reflected on the transistors which are the sameconduction type as the load MOS transistor and whose each mutualconductance is determined depending on the constant current.

At this time, the compensating circuit has a compensating elementconnected to the constant current node of the constant current source.The compensating element is one MOS transistor identical in size tocurrent control MOS transistors of one conduction type in each of thecomplementary MOS inverter type circuits. As another example, thecompensating circuit has a compensating element connected to theconstant current node of the constant source. The compensating elementis a MOS transistors equivalently smaller in size than the currentcontrol MOS transistors of one conduction type in the complementary MOSinverter type circuit. The equivalently small-sized MOS transistors areequivalent to MOS transistors connected in series in plural form, whichare identical in size to the current control MOS transistors of oneconduction types in the complementary MOS inverter type circuits. As afurther example, the compensating circuit comprises a current mirrorcircuit which supplies a mirror current to the constant current node ofthe constant current source. The current mirror circuit comprises pchannel type MOS transistors identical in size to the p channel typecurrent control MOS transistors in the complementary MOS inverter typecircuit, and an n channel type MOS transistor identical in size to the nchannel type current control MOS transistors in the complementary MOSinverter type circuit.

[4] As a specific form according to another aspect of the presentinvention, the delay circuit is configured as a timing generator whichdelays an input at the delay stage to output a timing signal. Forexample, a semiconductor integrated circuit has a memory equipped withthe delay circuit. The memory performs a read operation using the timingsignal generated by the delay circuit. As another specific form, thesemiconductor integrated circuit includes the memory and a logic circuitwhich access-controls the memory. According to a further aspect, thedelay circuit may be a ring oscillator which feeds back the output ofthe delay stage to the input thereof to generate a clock.

[5] In a specific form in which attention is focused on the constantcurrent source, the constant current source has a MOS transistor ofwhich the gate-to-source voltage is set in such a manner that thedifference in current between the drain and source due to the differencein temperature becomes small. In order to set the gate-to-sourcevoltage, a trimming register which loads trimming data therein, and adigital-to-analog converter which digital/analog-converts the trimmingdata loaded into the trimming register are provided. A voltage outputtedfrom the digital-to-analog converter defines a gate voltage to beapplied to the MOS transistor of the constant current source. In regardto the loading of the trimming data, a non-volatile memory area whichretains trimming data, and a control circuit which reads the trimmingdata from the non-volatile memory area in response to a reset and loadsthe data into the trimming register, may be provided.

Advantageous effects obtained by a representative one of the inventionsdisclosed in the present application will be explained in brief asfollows:

When a current that flows through a compensating circuit variesaccording to various conditions, a delay time of a delay stage iscontrolled by a current obtained by subtracting the current from aconstant current given from a constant current source. Therefore, it ispossible to realize a semiconductor integrated circuit equipped with adelay circuit which is reduced in dependence of a delay characteristicon a variation in power supply voltage, a variation in temperature andprocess variations.

If the delay circuit is used in the generation of a read timing for amemory, then it becomes easy to start up a sense amplifier with timingprovided to sufficiently increase the difference (read margin) inpotential between read data and a reference level. It is also possibleto suppress a reduction in reading speed due to read timing beingexcessively late.

Thus, a circuit operating speed can be rate-controlled at asubstantially constant speed, thereby making it possible to contributeto the operation of a circuit stably and at high speed. Aninternally-generated clock frequency can be rate-controlledsubstantially constant, thereby making it possible to contribute to theoperation of the circuit in high performance.

In the delay circuit using the constant current source, the compensatingcircuit may be configured of one compensating MOS transistor. Thus, acircuit area can be reduced as compared with a circuit or the like thatneeds a divider, a phase comparator and a charge pump. Since a crystaloscillator or the like for generating a standard clock is alsounnecessary, an increase in the number of parts can also be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing one example of a delay circuiton-chipped to a semiconductor integrated circuit according to thepresent invention;

FIG. 2 is an explanatory diagram illustrating relationships among acompensating element current Id flowing through a compensating MOStransistor and operating currents Ip of CMOS inverter type circuits,with respect to respective parameters in the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing another example of the delay circuiton-chipped to the semiconductor integrated circuit according to thepresent invention, which is equipped with a compensating circuit inwhich three compensating MOS transistors are connected in series;

FIG. 4 is a circuit diagram showing a further example of the delaycircuit on-chipped to the semiconductor integrated circuit according tothe present invention, wherein a compensating circuit comprises acurrent mirror circuit that supplies a mirror current to a constantcurrent node of a constant current source;

FIG. 5 is a circuit diagram depicting yet another example of the delaycircuit on-chipped to the semiconductor integrated circuit according tothe present invention, wherein the exchange of functions based on nchannel and p channel type MOS transistors is effected on a delaycontrol circuit shown in FIG. 1;

FIG. 6 is a circuit diagram showing a still further example of the delaycircuit on-chipped to the semiconductor integrated circuit according tothe present invention, wherein the exchange of functions based on ncannel and p channel type MOS transistors is effected on a delay controlcircuit shown in FIG. 4;

FIG. 7 is a timing chart illustrating delay variations in output OUT ofeach of the delay circuits described based on FIGS. 1 through 6 withrespect to an input IN thereof;

FIG. 8 is an explanatory diagram illustrating an inverter series delaycircuit according to a comparative example of the present invention, anddelay variations in output OUT thereof with respect to an input INthereof;

FIG. 9 is a circuit diagram showing a comparative example wherein adelay time is controlled by a constant current of a constant currentsource and no compensating circuit is adopted;

FIG. 10 is an explanatory diagram showing the principle of a constantcurrent source;

FIG. 11 is a block diagram illustrating a circuit for trimming a gatebias voltage of a constant current source MOS transistor;

FIG. 12 is a flowchart illustrating a process for writing trimming datainto a flash memory;

FIG. 13 is a flowchart illustrating a procedure for a read/load processof the trimming data at reset;

FIG. 14 is a block diagram illustrating a configuration which causes aflash memory equipped with a delay circuit to hold trimming data andmakes it available;

FIG. 15 is a block diagram showing a microcomputer illustrative of oneexample of a semiconductor integrated circuit according to the presentinvention;

FIG. 16 is a block diagram depicting a flash memory module mounted inthe microcomputer;

FIG. 17 is a timing chart illustrating read operating timings of theflash memory module;

FIG. 18 is a circuit diagram showing a delay circuit configured as aring oscillator; and

FIG. 19 is a timing chart illustrating a speed-best state (largefrequency) of an oscillation frequency produced from the ring oscillatorshown in FIG. 18 and a speed-worst state (small frequency) thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One example of a delay circuit on-chipped to a semiconductor integratedcircuit according to the present invention is shown in FIG. 1. The delaycircuit 1 shown in the same drawing comprises a delay stage 2 and adelay controller 3. The delay stage 2 comprises a plurality of CMOSinverter type circuits (complementary MOS inverter type circuits) 4connected in series. Each of the CMOS inverter type circuits 4 has aconfiguration wherein p channel and n channel switching MOS transistorsM1 and M4 are series-connected to p channel and n channel currentcontrol MOS transistors M2 and M3. The gates of the switching MOStransistors M1 and M4 of the first-stage CMOS inverter type circuit 4are supplied with an input signal IN. Thus, the common drains of thecurrent control MOS transistors M2 and M3 of the pre-stage inverter typecircuits 4 are sequentially connected to their corresponding gates ofthe switching MOS transistors M1 and M4 of the next-stage inverter typecircuits 4. Control voltages Vp and Vn for determining mutualconductance are applied to the respective current control MOStransistors M2 and M3 constituting the delay stage 2.

The delay controller 3 has an n channel type constant current source MOStransistor M5 that constitutes a constant current source. The drain ofthe n channel type constant current source MOS transistor M5 isconfigured as a constant current node Nconst. The constant currentsource MOS transistor M5 is gate-biased by a voltage Voutg to cause aconstant current Iconst to flow therethrough. A p channel type MOStransistor (load MOS transistor configured as a current source MOStransistor for a current mirror) M6 whose drain and gate areshort-circuited is connected to the constant current node Nconst. Adrain voltage of the MOS transistor M6 is connected to the gates of thecurrent control MOS transistors M2 as the control voltage Vp to therebymirror-reflect a current Ip flowing through the MOS transistor M6 on thecurrent control MOS transistors M2. In order to produce the controlvoltage Vn, there are provided a p channel type MOS transistor M7 whosegate is connected to the constant current node Nconst, and an n channeltype MOS transistor (current source MOS transistor for current mirror)M8 connected in series with the p channel type MOS transistor M7 andwhose gate and drain are short-circuited. A drain voltage of the MOStransistor M8 is connected to the gates of the current control MOStransistors M3 as the control voltage Vn so that a current Ip flowingthrough the MOS transistors M7 and M8 is mirror-reflected on the currentcontrol MOS transistor M3. A p channel type compensating MOS transistorM9 held in an on state is provided between the constant current nodeNconst and a power supply terminal Vdd as one example of a compensatingcircuit 5. The compensating MOS transistor M9 has a gate connected to acircuit's ground voltage VSS and is always held on. Element constants ofthe p channel type and n channel type MOS transistors M5 through M9 thatconstitute the delay controller 3 are made identical to elementconstants of p channel type and n channel type MOS transistorsconstituting a logic section as typified by the MOS transistors M1through M4 of the delay stage 2.

A current Id that flows through the compensating MOS transistor M9depends on the power supply voltage (Vdd), temperature (Ti) andthreshold voltage (Vth) of each MOS transistor. The threshold voltageprincipally varies according to process variations. The current Ip thatflows through the MOS transistor M6 is expressed in an equation ofIp=Iconst−Id. The current Ip is mirror-reflected on the MOS transistorsM7 and M2 by a current mirror circuit. The current Ip that flows throughthe MOS transistor M8 is also mirror-reflected on the MOS transistors M3by the current mirror circuit. When a variation in the power supplyvoltage and a variation in temperature or the like occur, thecharacteristic of the MOS transistor M9 changes and the current Idchanges correspondingly. Although the characteristics of the MOStransistors constituting the delay stage 2 are also intended to changein a similar manner at this time, the current Ip changes in thedirection to cancel it in response to the change in the current Id. Inbrief, when the on resistances of the MOS transistors constituting thedelay stage 2 and the like are intended to change due to the variationin temperature or the like, the on resistances of the MOS transistors M2and M3 are dynamically varied so as to cancel out influences produceddue to the changes in the on resistances. Relationships among thecompensating element current Id flowing through the compensating MOStransistor and the operating currents Ip of the CMOS inverter typecircuits, with respect to respective parameters in the circuit shown inFIG. 1 are illustrated in FIG. 2, for example. As the power supplyvoltage Vdd becomes high, the compensating element current Id increasesand the operating currents Ip decrease. As the temperature Ti becomeshigh, the compensating element current Id decreases and the operatingcurrents Ip increase. As the threshold voltage Vth becomes low, thecompensating element current Id decreases and the operating currents Ipincrease. As a drain-to-source saturation current Ids becomes large, thecompensating element current Id increases and the operating currents Iddecrease.

Thus, the delay stage 2 changes in its delay characteristic in such amanner that the influences such as the changes in the temperature andpower supply voltage at the above time are canceled out, and issubjected to suppression of a variation in delay time. In general, acircuit that needs a given amount of delay is configured of a delaycircuit and other logic section (decode section for selecting a mode orthe like, or the like). A given amount of delay is often needed intotal. Thus, the delay circuit 1 is configured of MOS transistorsidentical to other logic section, whereby the characteristic of thecompensating MOS transistor can also be adjusted such that the totaldelay becomes constant.

Since the compensating MOS transistor M9 is of the p channel type as isapparent from the circuit configuration shown in FIG. 1, the current Idthat flows through the compensating MOS transistor M9 depends on devicecharacteristics such as the threshold voltage of each p channel type MOStransistor, etc. and does not depend on a device characteristic of eachn channel type MOS transistor. In brief, the compensating MOS transistorM9 is ranked as a countermeasure suitable for the case in which avariation in device characteristic due to the power supply voltage,temperature and process variations noticeably occurs in each of the pchannel type MOS transistors as compared with the n channel type MOStransistors.

Another example of the delay circuit on-chipped to the semiconductorintegrated circuit according to the present invention is shown in FIG.3. The present example is different from the example shown in FIG. 1 inthat a compensating circuit 5 comprises three p channel typecompensating MOS transistors M9 connected in series. According to thecircuit shown in FIG. 3, a current Id that flows through thecompensating circuit 5 becomes smaller than one shown in FIG. 1. Thepresent circuit aims to proactively avoid the fact that when the currentsupply capacity of the compensating circuit 5 becomes excessively large,an increase or decrease in current Ip becomes sharp due to a largechange in current Id so that control is hard to converge. A compensatingMOS transistor small in gate width may be adopted. Since thecompensation is aimed to fine-adjust circuit characteristics, itnormally corresponds to Ip>Id. In the actual circuit, compensating MOStransistors connected in series or a compensating MOS transistor smallin gate width may be used.

A further example of the delay circuit on-chipped to the semiconductorintegrated circuit according to the present invention is shown in FIG.4. The present example is different from the example shown in FIG. 1 inthat a compensating circuit 5 comprises a current mirror circuit thatsupplies a mirror current to the constant current node Nconst of theconstant current source. The current mirror circuit constituting thecompensating circuit 5 comprises p channel type MOS transistors M11 andM12 identical in size to the p channel type current control MOStransistors M1 and M2 of each of the CMOS inverter type circuits 4, andan n channel type MOS transistor M13 identical in size to the n channeltype current control MOS transistors M3 and M4 of each of the CMOSinverter type circuits 4. A compensating element is of the n channeltype MOS transistor M13. A current Id that flows through thecompensating MOS transistor M13 depends on the threshold voltages of then channel type MOS transistors M3 and M4 of the CMOS inverter typecircuit 4 and does not depend on the threshold voltages of the p channeltype MOS transistors M1 and M2 of the same circuit 4. In brief, thecompensating circuit 5 shown in FIG. 4 is ranked as a countermeasuresuitable for the case in which a variation in device characteristic dueto a power supply voltage, temperature and process variations noticeablyoccurs in each of the n channel type MOS transistors as compared withthe p channel type MOS transistors.

With the connection of the compensating circuit 5 shown in FIG. 1 or 3and the compensating circuit 5 shown in FIG. 4 in parallel with eachother, although not shown in the drawing in particular, the currents Idthat flow through both compensating circuits as a whole depend on bothof the threshold voltages of the p channel type MOS transistors M1 andM2 and the threshold voltages of the n channel type MOS transistors M3and M4. Thus, even if, in this case, the variation in devicecharacteristic due to the power supply voltage, temperature and processvariations noticeably occurs in any of MOS transistors of p and nchannel types, such a configuration can adapt to it.

Yet another example of the delay circuit on-chipped to the semiconductorintegrated circuit according to the present invention is shown in FIG.5. Such a configuration as shown in the same drawing differs from theconfiguration of the delay controller 3 shown in FIG. 1 in that theconduction types of the MOS transistors constituting it are changed fromthe n channel type to the p channel type and from the p channel type tothe n channel type. A constant current source comprises a p channel typeMOS transistor M5 i. A compensating circuit comprises an n channel typeMOS transistor M9 i. Such a circuit configuration is suitable for a casein which a variation in device characteristic due to a power supplyvoltage, temperature and process variations noticeably occurs in each ofthe n channel type MOS transistors as compared with the p channel typeMOS transistors. Since only the n channel type MOS transistor M9 i isused for a compensating element, the present configuration is reduced incircuit area as compared with the configuration of FIG. 1.

A still further example of the delay circuit on-chipped to thesemiconductor integrated circuit according to the present invention isshown in FIG. 6. Such a configuration as shown in the same drawing isdifferent from the configuration of the delay controller 3 of FIG. 4 inthat the conduction types of the MOS transistors constituting it arechanged from the n channel type to the p channel type and from the pchannel type to the n channel type. A constant current source comprisesa p channel type MOS transistor M5 i. A compensating element comprises ap channel type MOS transistor M13 i. Such a circuit configuration issuitable for a case in which a variation in device characteristic due toa power supply voltage, temperature and process variations noticeablyoccurs in each of the p channel type MOS transistors as compared withthe n channel type MOS transistors.

According to the delay circuits 1 described based on FIGS. 1 through 6,a delay variation in output OUT relative to an input IN as illustratedin FIG. 7 is relatively small as indicated by DLY1 with respect to thevariation in power supply voltage, the variation in temperature and theprocess variations. In the case of a delay circuit which determines adelay time by the number of series stages of inverters as in acomparative example of FIG. 8, a delay variation in output OUT relativeto an input IN is relatively large as indicated by DLY2. When a delaytime is controlled by a constant current of a constant current sourceand no compensating circuit is adopted as in a comparative example ofFIG. 9, a delay variation in output OUT relative to an input IN is notreduced to FIG. 7 although it becomes smaller than one shown in FIG. 8.

The principle of the constant current source is shown in FIG. 10. In theconstant current source MOS transistor M5, the gate-to-source voltage(Vg) is set in such a manner that the difference in current between thedrain and source (Ids) due to the difference in temperature becomessmall. That is, as shown in the same drawing, such temperatureintersecting points that the drain-to-source currents relative to thethreshold voltages become identical substantially, exist under varioustemperatures typified by low and high temperatures. When the voltageslying in the neighborhood of the temperature intersecting points are setas gate voltages Voutg, it is possible to cause a constant current toflow into the constant current source MOS transistor M5 under thevarious temperatures without depending on the temperatures. Adjusting(trimming) the gate voltages Voutg every semiconductor integratedcircuits to which the delay circuits are on-chipped makes it possible tocause the constant current to flow without relying on processvariations. Thus, it is possible to obtain a constant current Iconstwhich does not depend on the power supply voltage, temperatures andthreshold voltages. Although not shown in the drawing in particular, thep channel type current source MOS transistor M5 i is also similar to theabove.

A circuit for trimming a gate voltage Voutg is illustrated in FIG. 11.Trimming data is loaded into a data register 10 through a data signalline IDB. The trimming data loaded into the data register 10 is suppliedto a digital-to-analog converter (D/A converter) 11. The D/A converter11 generates a gate bias voltage Voutg corresponding to the trimmingdata with a clamp voltage Cvdd generated by a clamp circuit 12 as a fullscale voltage. The clamp circuit 12 generates a reference voltage usingthe difference between threshold voltages of MOS transistors and effectsmultiplication on it through the use of a buffer amplifier to therebyform the corresponding clamp voltage Cvdd. The D/A converter 11 has, forexample, a resistance network of series resistors R and shunt resistorsr and takes a so-called R2R form circuit configuration wherein the clampvoltage Cvdd is applied to one ends of the respective shunt resistors rthrough CMOS switches SW turned on/off by signals of bits correspondingto the trimming data. The CMOS switches SW are switch-controlled by thecorresponding bits of the data register 10. Since the output of the D/Aconverter 11 is low impedance, the gate bias voltage Voutg is suppliedto its corresponding MOS transistor M5 through a voltage followeramplifier (VFAMP) 13.

The trimming data loaded into the trimming data register 10 is stored ina fuse program circuit or an electrically reprogrammable or rewritablenon-volatile memory typified by a flash memory. The setting of thetrimming data relative to a fuse program can be performed by selectivefusion or the like by laser irradiation in a test process of asemiconductor integrated circuit. Timing provided to load the trimmingdata from the fuse program circuit to the trimming data register may beperformed in sync with the reset of the semiconductor integratedcircuit. The fuse program circuit may be activated only upon its reset.

On the other hand, the writing of the trimming data into the flashmemory may electrically be performed through a tester in the testprocess or the like. Its write procedure is illustrated in FIG. 12. Anaddress for a trimming information area is latched in an addressregister (S1), and the trimming data is latched in a write data register(S2). A write voltage is applied to its corresponding address arealatched in the address register in accordance with the write data in thedata register (S3). Then, verify data is read from the address area(S4), and rewritten data is computed using the read verify data (S5). Itis determined whether the verify data coincides with the write data(S6). Steps S3 through S6 are repeated until the coincidence is obtainedat this determination. A procedure for a read/load process of thetrimming data at reset is shown in FIG. 13. When power-on reset isinstructed, a word line for the trimming information area of the flashmemory is selected, and the trimming data is transferred from thetrimming information area to the trimming data register. This processingis completed during a period up to the release of reset. The setting ofthe trimming data may be performed on power reset.

The delay circuit 1 and the trimming data register 10 may be part of theflash memory or a functional module different from the flash memory.When the delay circuit 1 is used in a timing control circuit (timinggenerating circuit) 15 or the like of the flash memory as illustrated inFIG. 14, a trimming data area 16 may be assigned to a predeterminedmemory area of a flash memory array 17. Trimming data selected and readat the trimming data area 16 is amplified by an amplifier 18, followedby being loaded into the trimming data register 10. The selection of aword line in the trimming area by an address decoder 19 is enabled inresponse to instructions for a reset operation based on a reset signalRESET, or by the supply of an address signal ADRt for selecting thetrimming area in a predetermined operation mode such as trimming datawriting or the like to the trimming data area.

A single chip microcomputer also called a data processor or amicroprocessor or the like illustrative of one example of asemiconductor integrated circuit according to the present invention isillustrated in FIG. 15.

Although not restricted in particular, the microcomputer 21 shown in thesame figure is formed over one semiconductor substrate (chip) likemonocrystalline silicon by the known semiconductor integrated circuitmanufacturing technology.

The microcomputer 21 includes a central processing unit (also calledCPU) 22, a random access memory (also called RAM) 23 employed in a workarea or the like of the CPU 22, a phase locked loop circuit (also calledPLL) 24 which generates an operation reference clock signal or the like,a flash memory module 25, a direct memory access controller (also calledDMAC) 26, a timer 27 and input/output ports 28 and 29. Although notrestricted in particular, the flash memory module 25 stores operationprograms or data of the CPU 22 therein. Those circuits are connected toone another by an internal bus 30. Although not restricted inparticular, a bus master for the internal bus 30 and an external busbelongs to the CPU 22 or DMAC 26. In a state in which the microcomputer21 is being mounted to a system, the CPU 22 effects erasure and writingon the flash memory module 25. Upon a device test or at a manufacturingstage, an external write device is capable of directly controllingerasure and writing on the flash memory module 25 through the ports 28and 29. External power supplies of the microcomputer 21 are configuredas a power supply voltage Vdd and a circuit ground voltage VSS. Acrystal oscillator or the like is connected to external terminals XTALand EXTAL. An original oscillation signal generated thereby is dividedby the PLL 24, which in turn is used as an internal reference clocksignal. A standby signal STBY, a reset signal RES and a mode signal MDor the like are inputted as external control signals. After power-on,the interior of the microcomputer 21 is initialized during a low levelof the reset signal RES. When reset is released by a high level of thereset signal RES, the CPU 22 starts execution of a program in a programarea designated by a vector at an address 0 or the like.

A block diagram of the flash memory module 25 is illustrated in FIG. 16.The flash memory module 25 has a memory mat 31 wherein a large number ofnon-volatile memory cells are arranged in matrix form. Selectionterminals of the non-volatile memory cells are connected to theircorresponding word lines WL or the like. Data terminals of thenon-volatile memory cells are connected to their corresponding bit linesBL and source lines SL or the like. A write latch circuit 32 employed indata writing in units of the word lines WL is connected to the bit linesBL. A column selector circuit 33 selects corresponding bit lines inaccordance with external input/output units of data. Data read from thebit line BL selected by the column selector circuit 33 is amplified by asense amplifier circuit 34, which in turn is outputted to the outsidefrom an input/output circuit 35. Write data sent from outside is latchedin the write latch circuit 32 through the bit line BL selected by thecolumn selector circuit 33, so that wiring into the correspondingnon-volatile memory cell is performed in the word line units. Erasure isperformed in units of a predetermined number of word lines, for example.A power circuit 36 generates high voltages necessary for writing anderasure. A timing control circuit (timing generator) 37 controls write,erase and read operations in sync with a clock CLK. Although notrestricted in particular, instructions for processing are given in theform of commands from the CPU 22 through an internal data bus 30D. Thetiming control circuit 37 interprets the commands and gives operationcontrol signals to the respective parts. A decoder/driver circuit 38used as a logic circuit controls the selection and driving of each wordline WL or the like and the operation of selection of the columnselector circuit 33 in accordance with the read, erase or writeoperation. Which word line WL should be selected in those selectingoperations is instructed by an address signal supplied through aninternal address bus 30A. Incidentally, the address bus 30A and the databus 30D are included in the internal bus 30.

In the present example, the delay circuit 1 is used to generate anactivation control signal (sense amplifier start signal) φsa or the likefor a plurality of sense amplifiers SA that constitute the senseamplifier circuit 34. The delay time set by the delay circuit 1 isdefined as a delay time required to obtain delay timing necessary from achange in clock signal CLK to a change in sense amplifier start signalφsa. Initial loading of trimming data into a data register 10 isperformed in response to power-on reset or the like in like manner asdescribed in FIG. 14.

Read operation timings of the flash memory module 25 are illustrated inFIG. 17. When the operation of the flash memory module 25 is selected inaccordance with a module select signal MSEL, the flash memory module 25selects a corresponding word line WL in sync with the rising edge of theclock CLK and performs precharge of its corresponding bit line BL by aprecharge signal φpc. The timing provided to raise a sense amplifierstart signal φsa relative to the rising edge of the clock signal CLK isdetermined using the delay time of the delay circuit. That is, the delaycircuit 1 inputs or receives the clock signal CLK as a signal INfollowing the rising edge of the module select signal MSEL. The controlcircuit 37 brings the sense amplifier start signal φsa to an enablelevel corresponding to a high level in sync with the rising edge of anoutput signal OUT of the delay circuit 1 during a predetermined period.Thus, the activated sense amplifier amplifies the potential of the bitline BL with respect to a reference potential ref and outputs read datacorresponding to the result of amplification to the data bus 30D.

As described above, the delay circuit 1 suppresses low the variation indelay characteristic due to the variation in power supply voltage, thevariation in temperature and the process variations. Thus, there are noproduced an event that the delay set by the delay circuit 1 becomesinsufficient so that the timing provided to activate the sense amplifierbecomes excessively early, whereby a margin sufficient for a senseoperation (for timing of ti) cannot be ensured, and an event that thedelay set by the delay circuit 1 becomes excessively large so that thetiming provided to activate the sense amplifier becomes excessivelyslow, whereby a read operation speed (at a time tj) is reduced. Thus,since the operation speed for data reading becomes constant with a highdegree of accuracy, this can contribute to high performance and speedingup of a memory. Further, the delay circuit 1 needs not provide adivider, a phase comparator and a charge pump in order to suppressvariations in delay characteristic, and is not increased in its area.Since there is no need to generate a standard clock through the use ofexternal parts such as a crystal oscillator for suppressing thevariations in delay characteristic, the number of circuit's parts doesnot increase either.

An example wherein a delay circuit is configured as a ring oscillator 6,is shown in FIG. 18. The present example is different from FIG. 1 inthat a plurality of CMOS inverter type circuits 4 are feedback-connectedat the delay stage 2 to configure an oscillation stage. An AND gate 7 isprovided for controlling start/stop of an oscillating operation. Symbolenable indicates an oscillation enable signal and enables theoscillating operation at a high level. A delay controller 3 serves so asto suppress variations in oscillating characteristic due to a variationin power supply voltage, a variation in temperature and processvariations, i.e., a variation in frequency. Since the operating currentof each of the CMOS inverter type circuits 4 is controlled using acurrent Ip that compensates for dependence on the variation in powersupply voltage, the variation in temperature and the process variations(variation in threshold voltage), an unillustrated circuit operated insync with a clock signal Ringout generated by the oscillator 6 iscapable of reducing the difference in operating speed between a speedbest state (large frequency) and a speed worst state (small frequency)as illustrated in FIG. 19 by way of example. Thus, since the frequencyof the clock signal generated inside can be kept constant with highaccuracy if the present invention is configured as the ring oscillator6, the circuit operated in sync with such a clock signal can be broughtto high performance.

While the invention made above by the present inventors has beendescribed specifically based on the embodiments, the present inventionis not limited to the same. It is needless to say that various changescan be made thereto within the scope not departing from the gistthereof.

The delay circuit can be applied not only to, for example, the usethereof in the generation of the sense amplifier activation signal ofthe memory but also to the generation of other timing control signals ofthe memory and the generation of control signals of various logicalintegrated circuits other than the memory. The memory to which thepresent invention is applied, is not limited to the rewritablenon-volatile memory typified by the flash memory. The present inventioncan be applied even to a random access memory, a mask ROM, etc. Further,the flash memory is not limited to the flash memory module on-chipped tothe microcomputer. The present invention can obviously be applied evento a discrete flash memory chip. The present invention is not limited tothe CMOS circuit. A MOS inverter type using a saturation load may beadopted. The delay stage may be configured using bipolar transistors.The compensating circuit may change its compensating element accordingto the circuit elements constituting the delay stage. The trimming datais not limited to such a configuration that it is held in the memoryhaving the delay circuit. In response to the reset instructions, thetrimming data may be initially loaded from the flash memory retainingthe trimming data to the random access memory or the like.

1. A semiconductor integrated circuit comprising: a delay circuit,wherein the delay circuit has a constant current source, a delay stage,and a compensating circuit, wherein said delay stage determines anoperation delay time of an output relative to an input depending on aconstant current produced by the constant current source, and whereinsaid compensating circuit compensates for a variation in delaycharacteristic of the delay stage due to a variation in temperature, avariation in power supply voltage and process variations in the oppositedirection. 2-21. (canceled)